1. Field of the Invention
The present invention relates generally to trellis-coded communications systems, and more specifically to Viterbi decoder having a high processing speed.
2. Description of the Related Art
A Viterbi decoder with a code rate 1/2 and a constraint length 3 (four metric states) is disclosed in Japanese Laid-Open Patent Specification Hei-6-303153. The disclosed decoder includes a branch metric calculator and a pair of add/compare/select (ACS) circuits to which the outputs of the branch metric calculator are supplied on a time-shared basis. The outputs of the ACS circuits are stored back into memories as intermediate results of an ACS process to be updated with new branch metrics from the calculator. A maximum likelihood decision circuit compares path metrics from the ACS circuits to select path metrics of the most likely path in the trellis diagram.
In most data communication systems, however, the constraint length is usually 7 which implies that the metric states amount to as large as 64. If a Viterbi decoder with constraint length 7 were implemented using the prior art technique, it would be necessary to provide as many connections for the data path of the path metrics as there are state metrics. Since the access to the path metric memories is a dominant factor on the overall performance of the Viterbi decoder, a long queue would be formed in the ACS circuits if parallel mode of operation is implemented.